Semiconductor devices, such as static and dynamic random access memory, use thin metal interconnect lines to electrically link different parts of a microcircuit. Downward scaling of these interconnects introduces severe concerns about the performance and reliability of the chip. One of the most compelling problems is void nucleation and growth, which degrades the electrical conductivity and eventually severs the interconnect line rendering the device inoperative. Void nucleation and growth result from mass transport and deformation. Thermal stresses and electric current are the main driving forces for void nucleation and subsequent growth.
In this paper we introduce a formulation to describe the evolution of defects driven by electromigration and thermal stresses on narrow interconnect lines. The methodology is based on a mixed discrete/continuum formulation, which merges a local Monte Carlo scheme with a finite difference one. In agreement with experiment, simulations show that for an initial defect in a perfect crystal: (temperature effects only) the defect rounds and vacancies are absorbed into the lattice; (electromigration and temperature) the defect shape is altered due to the competition of surface diffusion driven by electromigration and thermal effects; (thermal stresses, electromigration and temperature) cracks appear at the defect surface inducing a region of high stress concentration, promoting further crack growth. The current methodology offers the ability to analyze the behavior of defects subjected to individual driving forces as well as the coupled scenarios.